The four FPGAs are all Spartan-3 4000 devices with FG676 packaging. The Xilinx code name is "3s4000fg676". The pinout of each FPGA is different. Additionally, although the SMBH is wired for parallel programming (SelectMap), only JTAG programming actually works (see below).

Therefore you must built bitfiles with StartupClk = JTAGClk. You must also "Drive DONE pin high". In EDK this means that the Bitgen Options File must contain:
-g DriveDone:Yes
-g StartUpClk:JTAGCLK
The default incoming clock frequency is 100MHz. You can reprogram this via the virtual lab, but you must do so every time you connect to the board. The SMBH clears the FPGA and clock configuration as soon as you disconnect! (If you need to disconnect and reconnect, keep at least one connection open as you do so.)
The most important pins are:
FPGA Number
Serial RX
Serial TX
SW Reset

0 (A)
1 (B)
2 (C)
3 (D)
Richard Pack provided a number of files to accompany the board. These include schematics, UCFs, and sample VHDL code. This is in SVN. The UCFs provide you with additional pin-out data.

Sample EDK Project

There is a sample EDK project in SVN. It includes a Microblaze CPU, block RAM and UART. The zip file contains four UCFs, one for each FPGA. It also includes "program-fpga.py", which demonstrates the relevant virtual lab features. The "build.sh" script will build the contents on any Linux machine with EDK 10.1. (Use "xps -nw smbhtest.xmp", "save make", "exit" first so the Makefile contains the correct paths.)

DDR Memory Driver IP Core

See SMBH Memory.

Virtual Lab Configuration

Board name "smbh4" is available via the virtual lab. The econfig file is as follows:
bitfile_megabytes = 16
info_text = SMBH
driver = smbh
board_dir = data/smbh
Note 1: there is a special driver ("smbh"). The XSVF driver can be used, but this only provides JTAG programming support. There is no access to the clock chip, no way to operate the reset lines, and no way to blank the FPGAs (other than sending a blank bitfile).

Note 2: you can't use the usual FX12 bit file (fx12-linux-hardware). You must use a special SMBH version (smbh-hardware). As for all FX12 bit files, you use Xilinx EDK 10.1 to build it.

Note 3: the same Linux kernel, root filesystem and embedded software is shared by the SMBH and all other FX12-based virtual lab devices.

Clock Chip

The SMBH includes a clock chip, part number IDT5V9885. There is a data sheet:

The FPGAs are connected to OUTs 2 through 5: OUT2 is FPGA A, OUT3 is FPGA C, OUT4 is FPGA B, and OUT5 is FPGA D. The internal configuration of the clock chip connects all of these outputs to PLL1, whose frequency can be programmed using the virtual lab:
    from vlab import smbh
    yield vl.connect("smbh")
    yield smbh.setPLL(vl, freq_mhz)
"setPLL" takes a frequency specified in MHz. You can give a fractional value. The minimum is about 10kHz, the maximum is about 250MHz. The clock chip does support higher frequencies, but only for LVDS outputs, i.e. not OUT2 or OUT3. Therefore, higher frequencies should be produced within the FPGAs using DCMs.

The procedure that calculates the register settings is in drvsmbh.c and is called SMBH_Clock_Calc. This relies on the clock chip being initialised with a default program which is also stored in drvsmbh.c. It was generated using the IDT "Programmable Clock" tool. This Java application is in SVN in the "virtual-lab/nonfree" directory ("MagicClock.jar"). The default configuration used in the virtual lab is also stored in "jack.idtclock".

There is a second default configuration, "rpack.idtclock", designed by Richard Pack. This is still programmed into the clock chip's EEPROM, and thus it is used when the board is powered on. However, the virtual lab software immediately replaces it as the board is initialised.

Other virtual lab features

You can clear the FPGA configuration memories quickly using:
    from vlab import smbh
    yield vl.connect("smbh")
    yield smbh.masterReset(vl)
which blanks the FPGAs and resets the clock chip to the default frequency of 100MHz.
You can control the "SW Reset" lines entering each FPGA using the "smbh.softwareReset" method.

Design Flaws in Version 1

  • The LEDs do not work.
  • The "power cycle" feature cycles the FX12 power. This means it is no use for rebooting the FPGAs. Fortunately they can be reset using the INIT_B and PROG_B lines.
  • Several FX12 pins must be hardwired to +3V3 or GND.
  • The clock output for the DDR memory should be connected to a differential pair. In fact, regular IOBs are used.
  • Slave parallel (SelectMap) programming does not work properly (but JTAG is still available). This is probably because individual BUSY and DONE wires need to run to each FPGA (possibly INIT_B too).
  • The schematic diagram of the "Mini Module Interface" shows CLK2 as connected to OUT1. In fact CLK2 is connected to OUT3. This is a good thing! OUT1 has very limited functionality. However the schematic should be corrected.
  • The DDR interface is not compatible with Xilinx Memory Interface Generator.
  • The DDR CLK output is not an LVDS pair.
  • There is no feedback loop from the SRAM clock.
  • There is no feedback loop for the DQS signal.
  • One SMBH board uses so much current under load that a 1-1 relationship between SMBH boards and power boards is necessary for correct operation.
The pins that need to be hardwired are:
  • The mode pins. M2 (J1-45) and M1 (J1-42) should be wired to +3V3.
  • M0 (J1-46) should be wired to GND.
  • The power cycle pin (J2-60) should be wired to +3V3 (unless this issue is fixed).
  • The clock chip interface pins TRST (J2-33) and SHUTDOWN (J2-35) should be wired to +3V3.
  • The clock chip interface pin I2C/JTAG (J2-36) should be wired to GND.
A revised version of the SMBH should fix the power cycle feature and the LEDs, and hard-wire some of the pins as described above. The parallel programming feature could also be fixed but it is possible that the problem is misunderstood. (We only really have experience with JTAG programming.)